28nm FPGA HSTL IO Standard Green RS Flip Flop Design for AI Based Processor
Manisha Bharti1 , Deepshikha Kumari2 , Puneet Chandra Verma3
Section:Research Paper, Product Type: Journal Paper
Volume-7 ,
Issue-8 , Page no. 305-308, Aug-2019
CrossRef-DOI: https://doi.org/10.26438/ijcse/v7i8.305308
Online published on Aug 31, 2019
Copyright © Manisha Bharti, Deepshikha Kumari, Puneet Chandra Verma . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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IEEE Style Citation: Manisha Bharti, Deepshikha Kumari, Puneet Chandra Verma, “28nm FPGA HSTL IO Standard Green RS Flip Flop Design for AI Based Processor,” International Journal of Computer Sciences and Engineering, Vol.7, Issue.8, pp.305-308, 2019.
MLA Style Citation: Manisha Bharti, Deepshikha Kumari, Puneet Chandra Verma "28nm FPGA HSTL IO Standard Green RS Flip Flop Design for AI Based Processor." International Journal of Computer Sciences and Engineering 7.8 (2019): 305-308.
APA Style Citation: Manisha Bharti, Deepshikha Kumari, Puneet Chandra Verma, (2019). 28nm FPGA HSTL IO Standard Green RS Flip Flop Design for AI Based Processor. International Journal of Computer Sciences and Engineering, 7(8), 305-308.
BibTex Style Citation:
@article{Bharti_2019,
author = {Manisha Bharti, Deepshikha Kumari, Puneet Chandra Verma},
title = {28nm FPGA HSTL IO Standard Green RS Flip Flop Design for AI Based Processor},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {8 2019},
volume = {7},
Issue = {8},
month = {8},
year = {2019},
issn = {2347-2693},
pages = {305-308},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=4828},
doi = {https://doi.org/10.26438/ijcse/v7i8.305308}
publisher = {IJCSE, Indore, INDIA},
}
RIS Style Citation:
TY - JOUR
DO = {https://doi.org/10.26438/ijcse/v7i8.305308}
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=4828
TI - 28nm FPGA HSTL IO Standard Green RS Flip Flop Design for AI Based Processor
T2 - International Journal of Computer Sciences and Engineering
AU - Manisha Bharti, Deepshikha Kumari, Puneet Chandra Verma
PY - 2019
DA - 2019/08/31
PB - IJCSE, Indore, INDIA
SP - 305-308
IS - 8
VL - 7
SN - 2347-2693
ER -
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Abstract
The flexible, reusable nature of FPGAs makes them a great fit for different applications, from driver development to data processing acceleration. FPGAs can be programmed for different kinds of workloads, from signal processing to deep learning and big data analytics. In this article, we focus on the use of FPGAs for Artificial Intelligence (AI) workload acceleration. To make this thing happen we have design FPGA based Flip Flop Design for AI Based Processor. Here we have designed energy efficient RS Flip Flop. In consideration of technology upgradation, we have used 5G frequency for calculating total power consumption from 1GHZ to 5 GHZ. We have used two different IO standard HSTL_I_12 and HSTL_II_18 with different voltage (0.970, 1.009, 0.986 and 0.998 Volt). During the experiment we have found by applying HSTL_I_12 we have reduced our total power consumption by 44.87% which is significant among all the analysis.
Key-Words / Index Term
FPGA, AI, HSTL, flip flop, 28nm.
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