Open Access   Article Go Back

Improved stability and access time Using Different 6T SRAM Cells at Low Voltage

Ashish Raturi1 , Kamlesh Bhatt2

Section:Research Paper, Product Type: Journal Paper
Volume-7 , Issue-7 , Page no. 298-301, Jul-2019

CrossRef-DOI:   https://doi.org/10.26438/ijcse/v7i7.298301

Online published on Jul 31, 2019

Copyright © Ashish Raturi, Kamlesh Bhatt . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

View this paper at   Google Scholar | DPI Digital Library

XML View
PDF Download

How to Cite this Paper

  • IEEE Citation
  • MLA Citation
  • APA Citation
  • BibTex Citation
  • RIS Citation

IEEE Style Citation: Ashish Raturi, Kamlesh Bhatt, “Improved stability and access time Using Different 6T SRAM Cells at Low Voltage,” International Journal of Computer Sciences and Engineering, Vol.7, Issue.7, pp.298-301, 2019.

MLA Style Citation: Ashish Raturi, Kamlesh Bhatt "Improved stability and access time Using Different 6T SRAM Cells at Low Voltage." International Journal of Computer Sciences and Engineering 7.7 (2019): 298-301.

APA Style Citation: Ashish Raturi, Kamlesh Bhatt, (2019). Improved stability and access time Using Different 6T SRAM Cells at Low Voltage. International Journal of Computer Sciences and Engineering, 7(7), 298-301.

BibTex Style Citation:
@article{Raturi_2019,
author = {Ashish Raturi, Kamlesh Bhatt},
title = {Improved stability and access time Using Different 6T SRAM Cells at Low Voltage},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {7 2019},
volume = {7},
Issue = {7},
month = {7},
year = {2019},
issn = {2347-2693},
pages = {298-301},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=4764},
doi = {https://doi.org/10.26438/ijcse/v7i7.298301}
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
DO = {https://doi.org/10.26438/ijcse/v7i7.298301}
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=4764
TI - Improved stability and access time Using Different 6T SRAM Cells at Low Voltage
T2 - International Journal of Computer Sciences and Engineering
AU - Ashish Raturi, Kamlesh Bhatt
PY - 2019
DA - 2019/07/31
PB - IJCSE, Indore, INDIA
SP - 298-301
IS - 7
VL - 7
SN - 2347-2693
ER -

VIEWS PDF XML
327 222 downloads 159 downloads
  
  
           

Abstract

Contradictory nature of read and write stability and stability with speed necessitates the use of FinFET device which has less statistical variability, sensitivity and more on current. In this work, we explored three different FinFET device structures. These structures are used to form three different 6T SRAM cells. All the simulations are done with the help of Sentaurus TCAD. Three SRAM cells are compared to reduce access time and enhance data stability. We found that ADSE FinFET SRAM achieve significant improvement in access time as compared to Underlap FinFET SRAM cell without degradation of cell stability. On the other hand High-k spacer SRAM cell shows noteworthy increase in stability over other two cells with somewhat slower response.

Key-Words / Index Term

ADSE, FinFET, High-k spacer SRAM, Underlap

References

[1]. Jawar Singh, Saraju P.Mohanty, Dhiraj K. Pradhan, “Robust SRAM Designs and Analysis,” Available at www.springer.com, 2013
[2]. J. J. Kim et al., “Relaxing Conflict Between Read Stability and Writ ability in 6T SRAM Cell Using Asymmetric Transistors,” IEEE EDL, vol. 30, no. 8, pp. 852-854, August 2009.
[3]. V. A. A. Goud et al, “Atomistic Tight-Binding Based Evaluation of Impact of Gate Underlap on Source to Drain Tunneling in 5nm Gate Length Si FinFETs,” IEEE DRC, p. 51,52, June 2013.
[4]. V. Trivedi, J. G. Fossum, and M. M. Chowdhury, “Nanoscale FinFETs with gate–source/drain underlaps,” IEEE Trans. Electron Devices, vol. 52, no. 1, pp. 56–62, Jan. 2005.
[5]. FinFET from Device to Architecture 2014 (online) Available: http://dx.doi.org/10.1155/2014/365689
[6]. Pankaj Kumar Pal, Shivam verma, B.K.kaushik, “Statistical variability and sensitivity Analysis of dual-k spacer FinFET,” IEEE Trans. On electronic devices and solid state circuits, 2015.
[7]. D. Pham, L. Larson, and J.-W. Yang, “FinFET device junction formation Challenges,” in Proc. Int. Workshop Junction Technol., May 2006, pp. 73–77.
[8]. C. R. Manoj and V. R. Rao, “Impact of high-κ gate dielectrics on the device and circuit performance of nanoscale FinFETs,” IEEE Electron Device Lett., vol. 28, no. 4, pp. 295–297, Apr. 2007.
[9]. P.K.Pal, B.K.Kaushik, and S.Dasgupta “Investigation of symmetric dual k spacer trigate FinFET from delay perspective,” IEEE Trans. on Electron Devices,” vol.61, no.11, pp-3579-3585, Nov.2014.
[10]. J.P.colinge, FinFET and Other Multi Gate Transistor, a series on Integrated Circuits and Systems,” Springer.com” August 2007
[11]. Sherif A. Tawfik, Zhiyu Liu, and Volkan Kursun, “ Independent gate and Tied – Gate FinFET SRAM circuits,” IEEE ICM - December 2007.