Several architectures have been suggested for efficient VLSI implementation of 2-D DWT for real-time applications. It is found that multipliers consume more chip area and increases complexity of the DWT architecture. Multiplier-less hardware implementation approach provides a solution to reduce chip area, lower hardware-complexity and higher throughput of computation of the DWT architecture. The proposed design outline is (i) priority must be given for memory complexity optimization over the arithmetic complexity optimization or reduction of cycle period and (ii) memory utilization efficiency to be considered ahead of memory reduction due to design complexity of memory optimization method. Based on the proposed design outline four separate design approaches and concurrent architectures are presented in this thesis for area-delay and power efficient realization of multilevel 2-D DWT. In this paper a multiplier-less VLSI architecture is proposed using new distributed arithmetic algorithm named CSD. We demonstrate that CSD is a very efficient architecture with adders as the main component and free of ROM, multiplication, and subtraction. The proposed architecture using CSD provides less delay and minimum number of slice compared the existing architecture.

Discrete Wavelet Transform, Canonic Signed Digit, Read Only Memory, Multiplier-less Technique

[1] Rakesh Biswas, Siddarth Reddy Malreddy and Swapna Banerjee, “A High Precision-Low Area Unified Architecture for Lossy and Lossless 3D Multi-Level Discrete Wavelet Transform”, Transactions on Circuits and Systems for Video Technology, Vol. 45, No. 5, May 2017.
[2] Satish S Bhairannawar, Rajath Kumar, “FPGA Implementation of Face Recognition System using Efficient 5/3 2D-Lifting Scheme”, 2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA).
[3] Maurizio Martina, Guido Masera, Massimo Ruo Roch, and Gianluca Piccinini, “Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT”, IEEE Transactions on Circuits and Systems—I: Regular Papers, Vol .62, No.8, and August 2015.
[4] S.G. Mallat, “A Theory for Multiresolution Signal Decomposition: The Wavelet Representation”, IEEE Trans. on Pattern Analysis on Machine Intelligence, 110. July1989, pp. 674-693.
[5] M. Alam, C. A. Rahman, and G. Jullian, ”Efficient distributed arithmetic based DWT architectures for multimedia applications,” in Proc. IEEE Workshop on SoC for real-time applications, pp. 333 336, 2003.
[6] X. Cao, Q. Xie, C. Peng, Q. Wang and D. Yu, ”An efficient VLSI implementation of distributed architecture for DWT,” in Proc. IEEE Workshop on Multimedia and Signal Process., pp. 364-367, 2006.
[7] Senthil singh C and Manikandan. M, “Design and Implementation of an FPGA-Based Real-Time Very Low Resolution Face Recognition System”, International Journal of Advanced Information Science and Technology, Vol. 7, No. 7, pp. 59-65, November 2012.
[8] Archana Chidanandan and Magdy Bayoumi, “Area-Efficient MDA Architecture for the 1-D DCT/IDCT,” ICASSP 2006.
[9] M. Martina, and G. Masera, ”Low-complexity, efficient 9/7 wavelet filters VLSI implementation,” IEEE Trans. on Circuits and Syst. II, Express Brief vol. 53, no. 11, pp. 1289-1293, Nov. 2006.
[10] M. Martina, and G. Masera, ”Multiplierless, folded 9/7-5/3 wavelet VLSI architecture,” IEEE Trans. on Circuits and syst. II, Express Brief vol. 54, no. 9, pp. 770-774, Sep. 2007.
[11] Gaurav Tewari, Santu Sardar, K. A. Babu, ” High-Speed & Memory Efficient 2-D DWT on Xilinx Spartan3A DSP using scalable Polyphase Structure with DA for JPEG2000 Standard,” 978-1-4244-8679-3/11/$26.00 ©2011 IEEE.
[12] B. K. Mohanty and P. K. Meher, “Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT”, IEEE Transactions On Signal Processing, VOL. 59, NO. 5, MAY 2011.
[13] B. K. Mohanty and P. K. Meher, “Efficient Multiplierless Designs for 1-D DWT using 9/7 Filters Based on Distributed Arithmetic”, ISIC 2009.
[14] R. Praisline Jasmi and Mr. B. Perumal, “Comparison of Image Compression Techniques using Huffman Coding, DWT and Fractal Algorithm”, 2015 International Conference on Computer Communication and Informatics (ICCCI -2015), Jan. 08 – 10, 2015, Coimbatore, INDIA.