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Voltage THD Reduction for Cascaded Multi-level Converter using Sliding Mode Control

Rupendra Saini1 , K. T. Chaturvedi2

Section:Research Paper, Product Type: Journal Paper
Volume-7 , Issue-5 , Page no. 1504-1507, May-2019

CrossRef-DOI:   https://doi.org/10.26438/ijcse/v7i5.15041507

Online published on May 31, 2019

Copyright © Rupendra Saini, K. T. Chaturvedi . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: Rupendra Saini, K. T. Chaturvedi, “Voltage THD Reduction for Cascaded Multi-level Converter using Sliding Mode Control,” International Journal of Computer Sciences and Engineering, Vol.7, Issue.5, pp.1504-1507, 2019.

MLA Style Citation: Rupendra Saini, K. T. Chaturvedi "Voltage THD Reduction for Cascaded Multi-level Converter using Sliding Mode Control." International Journal of Computer Sciences and Engineering 7.5 (2019): 1504-1507.

APA Style Citation: Rupendra Saini, K. T. Chaturvedi, (2019). Voltage THD Reduction for Cascaded Multi-level Converter using Sliding Mode Control. International Journal of Computer Sciences and Engineering, 7(5), 1504-1507.

BibTex Style Citation:
@article{Saini_2019,
author = {Rupendra Saini, K. T. Chaturvedi},
title = {Voltage THD Reduction for Cascaded Multi-level Converter using Sliding Mode Control},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {5 2019},
volume = {7},
Issue = {5},
month = {5},
year = {2019},
issn = {2347-2693},
pages = {1504-1507},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=4439},
doi = {https://doi.org/10.26438/ijcse/v7i5.15041507}
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
DO = {https://doi.org/10.26438/ijcse/v7i5.15041507}
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=4439
TI - Voltage THD Reduction for Cascaded Multi-level Converter using Sliding Mode Control
T2 - International Journal of Computer Sciences and Engineering
AU - Rupendra Saini, K. T. Chaturvedi
PY - 2019
DA - 2019/05/31
PB - IJCSE, Indore, INDIA
SP - 1504-1507
IS - 5
VL - 7
SN - 2347-2693
ER -

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Abstract

This paper presents a detailed harmonic analysis in terms of Total Harmonic Distortion (THD) for different power circuit topologies of multi-level inverter fed induction motor drives. The most common multilevel inverter topologies are the neutral-point-clamped inverter (NPC), flying capacitor inverter (FC), and cascaded H-bridge inverter (CHB). This work is to analyze the performance of all the power circuit topologies of multilevel inverter with various multi carrier PWM control techniques. Simulation and results shows that the superiority of these inverters over two-level pulse width modulation based inverter fed drives.

Key-Words / Index Term

Multi-level Converter, Pulse Width Modulation, Total Harmonic Distortion

References

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