There has been an increasing interest in the radiation immunity of circuits in recent years as modern integrated circuits operating in high radiation environment require careful attention to the soft errors resulting in bit upsets. These events are referred to as single-event upsets (SEUs). SEUs will become more severe as a result of technology scaling and play a pivotal role in memory system stability. Memory systems with lower sensitivity to SEUs offer better stability and reliability if ignored lead to catastrophic situations in fields such as medicine, aerospace, etc. Therefore, it has become crucial that the design of the memory arrays is SEU resilient. The proposed design achieves high soft-error tolerance for robust low power operation in high-radiation environments making use of the MTCMOS technique. Less leakage power consumption is an important reason why this technology is incorporated into larger systems such as memories. This, in turn, leads to improved efficacy along with reduced susceptibility to single-event upsets and lower power consumption.

Single Event Upset (SEU), rad-hardening (radiation hardening), Static Random Access Memory (SRAM), low power, Multi-threshold CMOS (MTCMOS)

[1] R. C. Baumann, “Radiation-induced soft errors in advanced semiconductor technologies,” IEEE Trans. Device Mater. Rel., vol. 5, no. 3, pp. 305–316, Sep 2005.
[2] J. L. Barth, C. Dyer, and E. Stassinopoulos, “Space, atmospheric, and terrestrial radiation environments,” IEEE Transactions on Nuclear Science, vol. 50, no. 3, pp. 466–482, 2003.
[3] Todd. R. Weatherford “Radiation effects in high speed III-V integrated circuits,” International Journal of High Speed Electronics and Systems Vol. 13, No.1 (2003) 277-292.
[4] P. E. Dodd and F. W. Sexton, “Critical charge concepts for CMOS SRAMs,” IEEE Trans. Nucl. Sci., vol. 42, no. 6, pp. 1764–1771, Dec. 1995.
[5] E.G. Stassinopoulos “The space radiation environment for electronics,” Proceedings of the IEEE Vol: 76, Issue: 11, Nov 1988.
[6] .R. Oldham and F.B. McLean, “Total ionizing dose effects in MOS oxides and devices,” IEEE Transactions on Nuclear Science, 50(3):483–499, June 2003.
[7] P. E. Dodd and L. W. Massengill, “Basic mechanisms and modeling of single-event upset in digital microelectronics,” IEEE Transactions on Nuclear Science, vol. 50, no. 3, pp. 583–602, 2003.
[8] Alexander Fish, LiorAtias, Adam Teman “ A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications ” IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Volume: 24, Issue: 8, Aug. 2016).
[9] Mohab Anis, Mohamed Elmasry “Multi-Threshold CMOS Digital Circuits: Managing Leakage Power,” 2003.
[10] S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, J. Yamada “1­V power supply high­speed digital circuit technology with multithreshold­voltage CMOS,” Issue 8, Volume 30, August 1995.
[11] S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS,” IEEE Trans. Comput. Aided Des., vol. 24, no. 12, pp. 1859–1880, Dec. 2005.
[12] Rashmi Deshmukh, Anagha Zade, Rasika Bhusari “Temperature Monitoring and Regulating System for Power Saving”, International Journal of Computer Sciences and Engineering, Vol.1, Issue.2, pp.36-37, 2013.
[13] Anil Pratap “Analysis of Full and Half Adder Using Different Logic Style”, International Journal of Computer Sciences and Engineering, Vol.4, Issue.1, pp.6-9, Feb 2016.
[14] Lior Atias, Adam Teman, and Alexander Fish, “Single Event Upset Mitigation in Low Power SRAM Design,” IEEE 28th Convention of Electrical and Electronics Engineers in Israel, 2014.