The problems while designing a communication module comes up during hardware implementation in terms of power, area and speed. This paper presents an efficient decimation filter optimized in terms of power and area for wideband Sigma-Delta (ΣΔ) A/D converters. A work flow for a rapid design of this optimized decimation filter in MATLAB, along with its implementation is presented. The design is suited particularly for filters with high decimation factor. The filter offers a decimation factor of 128 having input of 3 bits from over-sampled ΣΔ modulator. The ΣΔ modulator having an input of 0.8MHz and sampling rate of 208MHz provides oversampling by a factor of 128 and resolution of 12 bits. Techniques like transposed direct-form polyphase decomposition, pipelining, retiming, resource sharing and CSD encoding are used for efficient design. The filter offers reduced power consumption and thereby suited for multi-rate filter design in state of art Sigma-Delta Analog to Digital converters.

Sigma Delta, ADC, Decimation filter, CSD, Multi-rate filter

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