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FPGA Realization of PWM using HDL

V.V.S.Vijaya Krishna1

Section:Research Paper, Product Type: Journal Paper
Volume-7 , Issue-2 , Page no. 121-125, Feb-2019

CrossRef-DOI:   https://doi.org/10.26438/ijcse/v7i2.121125

Online published on Feb 28, 2019

Copyright © V.V.S.Vijaya Krishna . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: V.V.S.Vijaya Krishna, “FPGA Realization of PWM using HDL,” International Journal of Computer Sciences and Engineering, Vol.7, Issue.2, pp.121-125, 2019.

MLA Style Citation: V.V.S.Vijaya Krishna "FPGA Realization of PWM using HDL." International Journal of Computer Sciences and Engineering 7.2 (2019): 121-125.

APA Style Citation: V.V.S.Vijaya Krishna, (2019). FPGA Realization of PWM using HDL. International Journal of Computer Sciences and Engineering, 7(2), 121-125.

BibTex Style Citation:
@article{Krishna_2019,
author = { V.V.S.Vijaya Krishna},
title = {FPGA Realization of PWM using HDL},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {2 2019},
volume = {7},
Issue = {2},
month = {2},
year = {2019},
issn = {2347-2693},
pages = {121-125},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=3630},
doi = {https://doi.org/10.26438/ijcse/v7i2.121125}
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
DO = {https://doi.org/10.26438/ijcse/v7i2.121125}
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=3630
TI - FPGA Realization of PWM using HDL
T2 - International Journal of Computer Sciences and Engineering
AU - V.V.S.Vijaya Krishna
PY - 2019
DA - 2019/02/28
PB - IJCSE, Indore, INDIA
SP - 121-125
IS - 2
VL - 7
SN - 2347-2693
ER -

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Abstract

Pulse Width Modulation (PWM) is an essential technique for many electrical applications. It is mainly used for controlling DC power to an electrical device. It can be used in applications where its duty cycle is used to convey information over a communication channel. Though many software designs and hardware models are available for PWM, FPGA modules are reliable in terms of speed and complexity. Hardware optimization is possible in FPGAs. Hence work is focused to realize the PWM on FPGA. In this paper hardware model of PWM using HDL is presented. This model is designed using VHDL and implemented on VIRTEX FPGA Device. Simulation is carried using Xilinx ISE. The RTL Design is synthesized using Xilinx XST and the generated bit stream file is implemented on Virtex FPGA board.

Key-Words / Index Term

PWM, RTL, VHDL, FPGA

References

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